This application claims priority under 35 U.S.C. xc2xa7xc2xa7119 and/or 365 to 99-58763 filed in REPUBLIC OF KOREA on Dec. 17, 1999; the entire content of which is hereby incorporated by reference.
1 Field of the Invention
The present invention relates to an apparatus for operating on a large amount of data such as a digital signal processor or an operation apparatus for an electronic system, and more particularly, to an operation apparatus of a digital signal processor, capable of processing the instructions represented in a matrix form in order to process the large amount of data and a digital signal processor capable of performing matrix operations.
2. Description of the Related Art
Due to the development of the semiconductor industry, systems whose sizes are extremely small and which can be used for a long time with batteries of small capacity have appeared. In particular, power consumption and the sizes of the systems are the center of interest in a technical field such as personal radio communication systems and adhesive medical instruments, which includes hearing aids.
Digital signal processors, which process a large amount of data, have been significantly developed in the electronics industry, keeping pace with an information-oriented society. However, the power consumption of systems has been rapidly increased since the development has been achieved with priority to the improvement of the performance.
In general, data items are processed one by one in the digital signal processor. For example, when a 2xc3x972 matrix multiplication represented in Equation 1 is done, a general micro processor processes the multiplications one by one.                               [                                                    R1                                            R2                                                                    R3                                            R4                                              ]                =                              [                                                            R5                                                  R6                                                                              R7                                                  R8                                                      ]                    xc3x97                                    [                                                                    R9                                                        R10                                                                                        R11                                                        R12                                                              ]                        t                                              (        1        )            
Equation 1 is represented by a program performed by a general micro processor as follows.
CLR ACC
MULT R5 R9
ADD ACC R5
MULT R6 R10
ADD ACC R6
MV R1 ACC
CLR ACC
MULT R5 R11
ADD ACC R5
MULT R6 R12
ADD ACC R6
MV R2 ACC
CLR ACC
MULT R7 R9
ADD ACC R5
MULT R8 R10
ADD ACC R6
MV R3 ACC
CLR ACC
MULT R7 R11
ADD ACC R5
MULT R8 R12
ADD ACC R6
MV R4 ACC
In order to reduce the size of the above program, a xe2x80x9cMACxe2x80x9d function of performing a multiplication and an addition in one clock period is added to a lot of digital signal processors. The program performed by the digital signal processors to which the xe2x80x9cMACxe2x80x9d function is added is represented as follows. It is possible to reduce the time for performing the program and the size of the program by adding the xe2x80x9cMACxe2x80x9d function.
CLR ACC
MAC R5 R9
MAC R6 R10
ADD ACC temp
MV R1 ACC
CLR ACC
MAC R5 R11
MAC R6 R12
ADD ACC temp
MV R2 ACC
CLR ACC
MAC R7 R9
MAC R8 R10
ADD ACC temp
MV R3 ACC
CLR ACC
MAC R7 R11
MAC R8 R12
ADD ACC temp
MV R4 ACC
It is noted from the above program that only addresses increase and the xe2x80x9cMACxe2x80x9d function is periodically repeated. In order to effectively process the program, a repeat statement, xe2x80x9cRPTxe2x80x9d, and an automatic address increase function (for example, R5++) are used by conventional digital signal processors. Such functions can be effectively used for programs for operations such as matrix operations in which a plurality of repeat statements are required. The program to which the repeat statements and the automatic address increase functions are provided can be written as follows.
CLR ACC
RPT 2
MAC R5++ R9++
ADD ACC temp
MV R1 ACC
CLR ACC
RPT 2
MAC R5++ R11++
ADD ACC temp
MV R2 ACC
CLR ACC
RPT 2
MAC R7++ R9++
ADD ACC temp
MV R3 ACC
CLR ACC
RPT 2
MAC R7++ R11++
ADD ACC temp
MV R4 ACC
The size of the program performed by conventional digital signal processors is still large in spite of the above-mentioned improvements.
However, when the matrix is expressed using variables, the calculation of Equation 1 can be performed by only the following codes.
SETD 222
MULT X1 X2 X3
When a certain algorithm or a function is expressed by various instructions, a memory having a large capacity is required. Accordingly, a processor such as the digital signal processor consumes much power. This is because a significant amount of power consumed by the processor is consumed by the memory for reading the instructions.
Also, in a system using a built-in processor where the capacity of the instruction memory is limited and functions expressed by various instructions must be performed, all the required instructions may not be loaded in a chip. In this case, an external memory must be added and used for the system. Accordingly, more power is consumed. Therefore, when a certain function is expressed by various instructions, a time for which products can be used without recharge is reduced, the sizes of the products are enlarged and the prices of the products are raised, since various chips are used in portable electronic systems.
In a system which performs a vector operation such as a systolic array operation, it is possible to process a plurality of operations. In such a system, data items are processed at one time by including various operation apparatuses such as a multiplexer and an adder inside the chip. Such a method can improve the performance of the system, however, does not reduce the power consumption and the size of the chip. Also, the vector operation is effectively used for only some digital signal processing algorithms.
The present invention relates to a technology of guaranteeing a long operation time with a small amount of power consumption, which is essential for portability of electronic products. A large amount (between 50 and 80%) of power consumed by a processor such as a digital signal processor is consumed by a program memory for reading instructions. Since the power consumption by the memory is proportional to the size of the memory and the number of times that data is read from and written to the memory, it is necessary to reduce the number of times that data is read from the memory and the size of the memory in order to reduce the power consumption.
Since many signal processing algorithms can be simply expressed using a method of matrix representation, it is an object of the present invention to provide a matrix operation apparatus in a digital signal processor capable of reducing the size of the program memory and the number of times that instructions are read from the memory by applying the method of matrix representation for a method of data representation.
It is another object of the present invention to provide a digital signal processor capable of performing matrix operations.
Accordingly, to achieve the first object, there is provided an apparatus included in a digital signal processor, for performing matrix operations, comprising a data storage means for storing operand data comprising matrix data in the form of a circular linked list and operation result data, address generating means for sequentially generating addresses required for performing matrix operations, the addresses including a series of addresses of first operand data, a series of addresses of second operand data, and a series of stored addresses of operation result data, whereby the addresses are sequentially generated according to the contents of the instruction words performed by the digital signal processor, and an operation means for reading data positioned in the address generated by the data storage means and performing operations according to the contents of the instruction words.
The address generating means comprises a matrix address storage means for storing the addresses of the matrix data items in the form of the circular linked list and outputting a first matrix data address, a second matrix data address, and an operation result matrix data address according to the contents of the instruction words, an A address generator for receiving the first matrix data address from the matrix address storage means and sequentially generating the series of addresses of the first operand data according to the instruction words, a B address generator for receiving the second matrix data address from the matrix address storage means and sequentially generating the series of addresses of the second operand data according to the instruction words, and a C address generator for receiving the operation result matrix data address from the matrix address storage means and sequentially generating the series of stored addresses of the operation result data according to the instruction words.
To achieve the second object, there is provided a digital signal processor capable of performing matrix operations, comprising a program memory for storing a signal processing program, an instruction register for temporarily storing the instruction words fetched from the program memory, an instruction decoder for interpreting the instruction words stored in the instruction register and generating a control signal, a data storage means for storing operand data including matrix data in the form of a circular linked list and operation result data, an address generating means for sequentially generating the series of addresses of first operand data, the series of addresses of second operand data, and the series of stored addresses of operation result data, which are required for the matrix operation, according to the control signal, and an operation means for reading the data positioned at the address generated by the address generating means from the data storage means and performing operations according to the control signal.
The instruction decoder generates a control signal corresponding to a pipeline structure, comprising the steps of fetching the instruction words stored in the program memory and temporarily storing the fetched instruction words in the instruction register, generating the addresses of the first operand data and the addresses of the second operand data by the address generating means, reading the first operand data and the second operand data from the data storage means and moving the first operand data and the second operand data to the operation means, performing operations by the operation means and generating the stored address of the operation result data by the address generating means, and storing the operation result data output from the operation means in the data storage means.